module mult_bound_01(
		input   wire			CLK,
		
		//输入数据
		input   wire	[5:0]	A,
		input   wire    [7:0]	B,
		
		//结果输出
		output	reg		[13:0]	P
		);

wire	[13:0]	pp;

	lpm_mult	lpm_mult_component (
				.dataa (A),
				.datab (B),
				.result (pp),
				.aclr (1'b0),
				.sclr (1'b0),
				.clken (1'b1),
				.clock (1'b0),
				.sum (1'b0));
	defparam
		lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
		lpm_mult_component.lpm_representation = "UNSIGNED",
		lpm_mult_component.lpm_type = "LPM_MULT",
		lpm_mult_component.lpm_widtha = 6,
		lpm_mult_component.lpm_widthb = 8,
		lpm_mult_component.lpm_widthp = 14;
		
always @(posedge CLK)
	P <= pp;

endmodule		
